1. Field of the Invention
The present invention relates to field effect transistors and more particularly, to a method and system for reduction of OFF-current in field effect transistors.
2. Discussion of the Related Art
In general, field effect transistors are known to function where one of an electron or a hole plays a role of a carrier that contributes to electrical conduction. In addition, an oxide film is formed on a semiconductor layer and a metal layer is formed on the oxide film. Moreover, thin film transistors have been commonly used as switching elements in liquid crystal display (LCD) devices.
FIG. 1 is cross-sectional view of a field effect transistor according to the related art. In FIG. 1, the field effect transistor includes an active layer 2, an insulating layer 4, a gate electrode 8, a passivation layer 10, and source and drain electrodes 12 and 14. The active layer 2 is formed on a substrate 1, such as a glass or a wafer, and the insulating layer 4 is formed on the active layer 2. The gate electrode 8 is formed on the insulating layer 4, and the passivation layer 10 covers the gate electrode 8 and the insulating layer 4. The source and drain electrodes 12 and 14 contact the active layer 2 through the passivation layer 10 and the insulating layer 4. A source region “s” and a drain region “d” include impurity ions and are spaced apart from each other in the active layer 2. The impurity ions are not present within a channel region 3 located between the source region “s” and the drain region “d.” The source electrode 12 is connected to the source region “s” and the drain electrode 14 is connected to the drain region “d.” If a voltage is applied to the gate electrode 8 of the field effect transistor, carriers are driven into the channel region 3 and the source and drain electrodes 12 and 14 are in electrical communication with each other. A boundary between the source region “s” and the channel region 3 is commonly referred to as a source junction 2b, and a boundary between the drain region “d” and the channel region 3 is commonly referred to as a drain junction 2a. 
Amorphous silicon or polycrystalline silicon may be used for the active layer 2. Amorphous silicon has been commonly used for flat panel display devices, such as liquid crystal display (LCD) devices, since it can be easily deposited over large areas under low temperatures of about 350° C. However, many localized defects occur since amorphous silicon has disordered atomic arrangement and weak Si—Si bonding. Alternatively, polycrystalline silicon has ordered atomic arrangement and electric mobility 100 times as fast as amorphous silicon. However, polycrystalline silicon demonstrates large amounts of leakage currents due to trap boundaries of crystal grains. Accordingly, the defects of both amorphous and polycrystalline silicon materials eventually increase an OFF-current of the field effect transistor, thereby the source and drain electrode 12 and 14 are frequently in electrical communication even when the field effect transistor is a desired OFF-state. The increase of the OFF-current of the field effect transistor decreases an ON-current of the field effect transistor, thereby deteriorating device reliability. The OFF-current condition is considered more serious in the field effect transistor that uses polycrystalline silicon.
Thus, many structural methods have been suggested to overcome the OFF-current problems. For example, a field effect transistor having a dual gate structure or a multi-gate structure has been suggested. In addition, an off-set region may be fonned within a vicinity of the source and drain junctions, or a lightly-doped drain structure may be applied to the field effect transistor.
Alternatively, a method to reduce the OFF-current without changing the structure of the field effect transistor has been suggested. For example, the OFF-current can be reduced by generating an OFF-stress to each junction region using two AC (alternating current) voltage pulses to overcome the defects of the silicon active layer. The OFF-stress is generated in the junction regions by applying the AC (alternating current) voltage pulses respectively to the gate electrode and the drain electrode, respectively, as disclosed in U.S. Pat. No. 5,945,866, which is hereby incorporated by reference.
FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal panel for a liquid crystal display (LCD) device according to the related art. In FIG. 2, the liquid crystal panel has a gate line 32 disposed along a first direction and a data line 34 disposed along a second direction. The gate line 32 transmits a scan signal voltage and the data line 34 transmits an image signal voltage. Crossings of the gate and data lines 32 and 34 define pixel regions, and the field effect transistor and the liquid crystal capacitor CLC are formed at each of the pixel regions. A thin film transistor is commonly used for the field effect transistor because of its light weight and small dimensions. A gate electrode G of the field effect transistor is connected to the gate line 32, and a drain electrode D is connected to the data line 34. A source electrode S is electrically connected to a pixel electrode (not shown), which is commonly used as one of electrodes for applying a voltage to liquid crystal material (not shown).
Although not shown, the liquid crystal capacitor CLC comprises the pixel electrode, a common electrode, and the liquid crystal material that is disposed between the pixel electrode and the common electrode, wherein a common line 37 is connected to the common electrode. Since the liquid crystal display device usually displays images on a frame-by-frame basis, a voltage that is applied to the liquid crystal capacitor CLC must be maintained until a voltage for a next frame is applied to the liquid crystal capacitor CLC. Accordingly, a storage capacitor CSt is provided to preserve the voltage until the next voltage for the next frame is applied. The storage capacitor CSt is electrically connected in parallel to the liquid crystal capacitor CLC, and may be a storage-on-common type (SOC) storage capacitor CSt that has an additional storage line 36. The storage capacitor CSt serves to stabilize gray level, reduce flicker and residual image, as well as to preserve the signal. Accordingly, the two different AC voltage pulses are applied to the gate electrode G and the drain electrode D of the field effect transistor to reduce the OFF-current.
FIG. 3A is a graph of voltages applied to each electrode of a field effect transistor for reducing an OFF-current in the field effect transistor according to the related art, and FIGS. 3B and 3C are schematic diagrams illustrating voltage values of each electrode of the field effect transistor when the voltages of FIG. 3A are applied according to the related art. In FIGS. 3A to 3C, if a negative voltage of −10V (volt) is applied to the gate electrode G to turn the field effect transistor ON, an electric current flows from the drain electrode D to the source electrode S. Accordingly, a negative voltage of −10V (volt) is subsequently applied to the drain electrode D and is conducted to the source electrode S. Then, the field effect transistor is turned OFF by application of a positive voltage of +30V (volt) to the gate electrode, and a voltage of 0V (volts) is applied to the drain electrode D. Accordingly, the gate electrode G has a voltage value of +30V, the drain electrode D has a voltage value of 0V, and the source electrode S has a voltage value of −10 V, as shown in FIG. 3B. Thus, a significant potential difference exists between the gate electrode G and the drain electrode D, and a significant potential difference exists between the gate electrode G and the source electrode S. Accordingly, an OFF-stress phenomenon occurs at regions near to the drain and source junction 2a and 2b (in FIG. 1). A greater OFF-stress effect is expected to occur at the source junction 2b (in FIG. 1), which is shown in FIG. 3B as an arrow, since the potential difference between the gate electrode G and the source electrode S is larger than the potential difference between the gate electrode G and the drain electrode D. If a negative voltage of −10 V is applied to the gate electrode G again to turn the field effect transistor ON, then the source electrode S is discharged to have a voltage of 0V. Subsequently, a positive voltage of +30 V is applied to the gate electrode G to turn the field effect transistor OFF and a negative voltage of −10 V is simultaneously applied to the drain electrode D. As a result, there are potential differences between the gate electrode G and the drain electrode D, and between the gate electrode G and the source electrode S, as shown in FIG. 3C. Since the potential difference between the gate electrode G and the drain electrode D is larger than the potential difference between the gate electrode G and the source electrode S, a greater OFF-stress effect occurs at the drain junction 2a (in FIG. 1) than the source junction 2b (in FIG. 1). Accordingly, the process reduces the defect of the silicon active layer by generating the OFF-stress at the drain and source junctions 2a and 2b (in FIG. 1). The process uses two AC voltage pulses for the gate electrode G and for one AC voltage pulse for the drain and source electrodes D and S. However, it is not easy to control the period of the AC voltage pulses accurately with proper timing.